1. Field of the Invention
The present disclosure relates to a phase-locked loop and a delay-locked loop.
2. Discussion of Related Art
A phase-locked loop (PLL) refers to a system that controls an output signal using a phase difference between a reference signal and a signal which is obtained by frequency-dividing the output signal and then fed back. The PLL detects a phase difference between a frequency-division result of the output signal and an input signal, determines the detected phase difference as an error, and adjusts an input voltage of a voltage controlled oscillator so that the error may be reduced. In this way, an output frequency is changed.
When the phase difference between the input and the feedback of the output becomes 0, phases are locked, and the output signal is adjusted so that the locked state may be maintained. A frequency difference between the input and the output varies according to a frequency divider. The frequency of the output signal is controlled according to a division ratio of the frequency divider. In most PLLs, an output is oscillated at a higher frequency than an input.
During an operation of an analog PLL, a reference signal is provided as any one input of a phase frequency detector (PFD), and an output signal of a frequency divider having a different phase and/or frequency than the reference signal is provided as another input.
The PFD outputs an error signal by detecting a difference in phase and/or frequency between the reference signal and the output signal of the frequency divider. A charge pump (CP) receives the error signal and outputs a current signal corresponding to the error signal, and a loop filter (LF) outputs a control signal by eliminating unnecessary frequencies from the current signal to control a voltage controlled oscillator (VCO). The VCO outputs a signal having a frequency corresponding to the control signal output by the LF and provides the signal to the frequency divider for a feedback to the PFD.
A delay-locked loop (DLL) is a circuit used to change a phase of a clock signal. In general, a DLL is used as a clock buffer in an integrated circuit or used in a clock-data recovery (CDR) circuit. A DLL includes a delay chain in which a plurality of delay elements are cascaded. A signal provided as an input is delayed by the delay elements, and a signal having a target phase is output.